PERSONAL DETAILS
Date
of Birth: 21/06/69
Nationality: British/New
Zealand (dual)
SKILLS
Main
Skills:
Digital
Signal Processing algorithm design and implementation for digital
communications (radio modem design, (de)modulation/coding,
filtering, acquisition/tracking etc.).
3G
physical layer, especially chip rate processing and HSPA.
Communication
system modelling and simulation using Matlab, COSSAP, Mathcad etc.
Software
engineering including experience of the full software lifecycle on
several projects. Competent in architecture, design, implementation
and testing of multiprocessor real time systems.
Real
time embedded C including the use of real time kernels.
Preparation
of quality technical documentation (specifications,
feasibility/design documents etc.).
Secondary
skills:
C++,
Python, PERL, combined Matlab/C, assembler (esp. on TI C64xx DSPs),
MS Visual C++, TI Code Composer Studio, configuration management
tools.
Digital/analogue
hardware design.
Radio
systems design (propagation, transceiver architectures, on-air
protocols).
Languages:
French (advanced) and Mandarin (beginner).
EDUCATION AND QUALIFICATIONS
1999 Master
of Science in Electrical and Electronic Engineering (with
Distinction)
at University of Surrey, England; Part time study; subjects
included: Advanced DSP algorithms, Speech/Image Processing, Object
Oriented Design/C++, Mathematics, Modulation/Coding, Artificial
Intelligence Programming, Microprocessor Architectures; Final year
project: Design of tactical radio demodulator.
1998
Qualified MIEE
and CEng.
1991 Bachelor
of Electrical and Electronic Engineering (1st Class Honours); Auckland School of Engineering, Auckland University, New Zealand.
1990
Senior
engineering prize, Exicom
scholarship in communications engineering and best radio systems
project prize.
1988
State
scholarship in physics and mathematics.
PROFESSIONAL
EXPERIENCE
10/2007 onwards.
DSP Consultant on various projects. Main experience includes:
4G LTE
development (3GPP Releases 8 to 10)
- LTE receiver development.
3G
HSPA+
development (3GPP Releases 6 to 9)
This
work (and from 2000 to 2006) generally covers design, documentation,
implementation and testing of many features to aggressive time
scales. Most coding used real time embedded C on TI C64xx/C62xx DSPs.
Dual
cell and MIMO HSPA+ receivers including Matlab simulations. Ongoing
performance optimizations to algorithms until uncoded 64-QAM had
zero BLER in ideal conditions.
Integrating Matlab models
with a Matlab/C++ GUI. Developed related tools
in Python/Matlab.
Involved
in design and implementation of many release 6 to 9 features
(64-QAM, DTX/DRX operation, CQI table generation, HS-SCCH orders,
etc.).
System
architect for DC-HSUPA and multi-UE enhanced UL cell FACH features.
9/2006
to
9/2007
Real Time Embedded Engineer; Cambridge Silicon Radio, Cambridge, England.
System
on Chip:
10/2000
to
8/2006 DSP Engineer; Ubinetics Ltd, Cambridge, England.
TM100
/ TM500 (plus) / Multi-UE 3G Test Mobiles:
3GPP
compliant Searcher:
This substantial piece of physical layer software (~18000 lines of
C) provided robust inter/intra-frequency measurements, cell search,
ray tracking and other algorithms intended for use in real radio
channels on the TM500 plus test mobile. Designed with one other
person and implemented ~80% alone.
High
Speed Downlink Packet Access (HSDPA) Rake receiver:
This was the first commercial HSDPA receiver in the world and
successfully ran 14 Mbit/s over the air on the TM500 test mobile.
Co-authored a related patent, “Facilitating reference signal
cancellation”.
Multi-UE:
Involved in design and implementation of extensions to the TM500
test mobile to support up to 32 HSDPA mobiles, each with an
independent radio channel propagation model.
Matlab
simulation of a 3G mobile:
Responsible for signal acquisition and tracking algorithms,
simulation control software and MySQL database interface software.
TM100
Searcher:
Overall responsibility for design and implementation of original
‘searcher’ software on the TM100 test mobile. Implemented and
documented various CDMA algorithms including transmit diversity
detection, AFC, path searcher, Delay Locked Loop, cell search etc.
Complete responsibility for redesigning and improving original
prototype software.
9/1999
to 9/2000 Principal Engineer; Thales Research Ltd (Part of former
CSF-Thomson Racal).
TETRA
covert transceiver development:
Successfully
implemented Trans European Trunked Radio (TETRA) software.
Responsibilities included: Layer 2 (Lower MAC), Encryption
algorithms and Vocoder integration as well as other miscellaneous
DSP software. All programming in C and (less often) TMS C54X
assembler.
Worked
in 3 man DSP team coding and testing to an existing specification
with some software design and documentation.
9/1998
to 8/1999 Senior Engineer; Racal Research Ltd, Reading, England.
Tactical
modem study:
Developed
novel DSP algorithms for next generation tactical radio modem
(including QAM/GMSK (de)modulation, equalisation and signal
acquisition/tracking algorithms).
Designed
GMSK frequency hopping radio modem demonstrator using COSSAP.
4/1995
to 8/1998 Design Engineer; Racal Research Ltd, Reading, England.
In
charge of requirements capture, feasibility studies and initial
design for (TRACS) linear digital telemetry modem. Successfully
designed and simulated the modem in COSSAP using C.
Designed
digital hardware for modem board of military tactical radio.
Designed
and built Cartesian loop amplifier linearization circuit.
Produced
feasibility studies on short range radio propagation and other
areas.
1994
to 1995 Systems Engineer; Racal Messenger Ltd, Bracknell, England.
1991
to 1992 Project Manager; British Telecom plc, London, England.
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